A semiconductor device, in which a semiconductor-on-insulator (SeOI) region and a bulk semiconductor region are formed on an upper surface of a semiconductor base substrate, wherein the SeOI region comprises a buried insulating oxide layer (BOX) and a thin semiconductor layer, is known as a hybrid semiconductor device. Such a device may be used in memory cell.
FIG. 1 is a cross-sectional view of a known hybrid semiconductor device 101 like, for example, disclosed in Yamaoka et al., IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, pp. 2366-2372, Nov. 2006.
As shown in FIG. 1, the hybrid semiconductor device 101 includes a SeOI region 113 comprising a BOX layer 105 and a SeOI layer 107 formed on a bulk substrate 103 and a bulk semiconductor region 111 formed on the same bulk substrate 103. The SeOI region 113 and the bulk semiconductor region 111 are usually separated from each other by a shallow trench isolation (STI) 123.
Devices comprising SeOI regions offer several advantages over more conventional semiconductor devices. For example, SeOI devices may have lower parasitic capacitances and lower power consumption requirements than non-SeOI devices that perform similar tasks and thereby provide faster switching times for the resultant circuits. Since the SeOI region may be provided with an ultra-thin BOX layer, threshold voltage (Vt) may be controlled by changing the voltage of an underlying well and, hence, it enables back-gate control with low bias voltage. The back-gate bias is applied through a well contact formed through the BOX layer, wherein the wells within the SeOI region and the bulk semiconductor region are separated from each other by STIs.
However, the hybrid semiconductor devices such as the conventional device have the following drawbacks. Unlike the bulk semiconductor region, the body of the SeOI region is usually not connected to a specific reference potential that may allow minority charge carriers to accumulate in that region and, hence, a floating body potential may exist in the SeOI region. This phenomenon leads to a variation in the threshold voltage (Vt) of the semiconductor devices. In particular, for static random access memory (SRAM) cells, the threshold voltage fluctuations may result in significant instabilities of the devices, which may not be tolerable in view of data integrity of the memory cells.
Further, it is known to implant three different concentrations of dopants (n-type or p-type) in a given region to form a channel of a metal-oxide-semiconductor field effect transistor (MOSFET) in a bulk substrate. The three different concentrations of dopants lead to three levels of doping: a shallow level called “Vt-doping,” a deeper level called “ground plane” (GP) doping and an even deeper level called “well doping.” On the other hand, doping in the SeOI region is used to form the back side electrodes of the SeOI transistors. Formation of the back side electrodes is achieved with different implant conditions, thus, also with a different mask.
Therefore, the fabrication of a hybrid semiconductor substrate, comprising a SeOI region and a bulk semiconductor region, requires different implant conditions for each region. The process cost and time for the fabrication thus increases due to the need of a plurality of different masks to be able to carry out the implant steps in both the SeOI region and the bulk semiconductor region and, thereby, a greater number of process steps.